Semiconductor memory device
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United States of America Patent
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Jun 30, 1987
Issued Date -
N/A
app pub date -
Jul 1, 1986
filing date -
Mar 30, 1982
priority date (Note) -
Expired
status (Latency Note)
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Abstract
In a semiconductor memory cell having PNPN type memory cells, a vertical PNPN element is used as a load transistor and a sense transistor or a hold transistor, or both. A buried layer is used as a wiring layer for a word line or a bit line, so that the switching speed can be increased and the memory cell area can be decreased.
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