Process of forming integrated circuits with contact pads in a standard array
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United States of America Patent
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Aug 11, 1987
Issued Date -
N/A
app pub date -
Oct 9, 1986
filing date -
Mar 22, 1984
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
An integrated circuit chip includes a top layer of dielectric penetrated by conductive vias connecting electrical contacts within the integrated circuit proper to a network of electrical leads disposed on top of the dielectric layer; the network of leads, in turn, being connected to an array of contact pads adapted for simultaneous solder connection to a leadframe.
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