Power-down circuits for dynamic MOS integrated circuits
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Aug 11, 1987
Grant Date -
N/A
app pub date -
Mar 18, 1985
filing date -
Mar 21, 1984
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A power-down circuit for saving operational power dissipation of a dynamic MOS integrated circuit during idling conditions. A clock divider generates a divided clock signal in response to an internal clock signal inputted thereto. The divided signal is synchronized with the internal clock signal and has a repetition rate which is slower than that of the internal clock signal. A control circuit delivers the control signal when a triggering signal is inputted thereto. A clock selecting circuit transfers either the internal clock signal or the divided clock signal to the dynamic MOS integrated circuit in response to the control signal.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully