Importance

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Abstract

A process for two layer gold integrated circuit metallization is disclosed. The process includes electrodeposition of a first metal layer, preferably of gold, atop a barrier layer, followed by electrodeposition of a second metal layer or cap, atop the gold to form a first metallization layer. The cap is corrosion-resistant metal having a rigidity at annealing temperature greater than that of gold. Following annealing, a dielectric interlayer is deposited so as to fill the regions adjacent sidewalls of the first metallization layer. Vias are formed in the interlayer dielectric, a second barrier layer is deposited and photoresist is applied and patterned for electrodeposition of a second, gold metallization layer. During annealing, the rhodium cap retains the as-deposited shape of the gold in the first metallization layer to facilitate insulative spacing between the first and second metallizations and to insure complete filling of interlayer dielectric on the lower edges of the first metallization.

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First Claim