Two-wire bus-system comprising a clock wire and a data wire for interconnecting a number of stations
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United States of America Patent
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-
Aug 25, 1987
Grant Date -
N/A
app pub date -
Nov 2, 1981
filing date -
Oct 31, 1980
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A computer system comprises a number of stations which are interconnected by means of a clock bus wire (20) and a data bus wire (22) which both form a wired logic function of the signals generated thereon by the stations (32, 34). During the clock pulses, the signal on the data bus wire is stationary; it may change between the clock pulses. Start and stop conditions are formed by a signal combination between clock bus wire and data bus wire (60 and 62, respectively) which is not permissible in a data stream. If there is more than one master station so that a composite clock signal occurs on the clock bus wire, the clocks of the relevant master stations are each time resynchronized to the actual transitions in the composite clock signal.
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