Importance

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Abstract

Address circuitry generates groups of tag signals, and each group is associated with a data word in a data processing device. A portion of the tag signals defines an addressable location in a storage device and another portion of the tag signals defines an operational identification of its associated data word. As data words (i.e., instruction words, operands, etc.) are fetched from memory they are decoded, if necessary, or made ready, (for use by the circuitry which executes the operations intended for such instructions, operands, etc.), and are stored in a multi-plane set of buffers. Each of said buffers has a plurality of address locations, corresponding to the address locations defined by said first portions of said tag signals, and each of said planes is selectable by said other portions of said tag signals. Accordingly, all of the data words stored in one plane have the same operational purpose, for example such as each being first operand, and each data word addressable by the same address (albeit in different planes) is related to the same program manipulation. In view of the tag signals being associated with the data words, the fetching, decoding and storing of the data words can be accomplished in a non-sequential fashion, with reduced hardware and without the delayed actions which have accompanied pipeline operations (of the prior art), when one or more of the data manipulating stages, in such pipeline operations, is busy.

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First Claim