Importance

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Abstract

A process for the fabrication of semiconductor components and in particular a process in which the components are fabricated with a controlled spacing of etched channels. The process is in particular utilized in fabricating a monolithic array of elements such as a pin diode array. The process of the present invention combines the use of an anisotropic silicon etching process for the desired device geometries with a means of defining all device surface topology by substantially a single photomask thus eliminating critical mask alignment. A second embodiment of the invention is also described employing fewer layers of deposition with a double photomask step.

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First Claim