Microprocessor system having a multiplexed address/data bus which communicates with a plurality of memory and input/output devices including TTL output gates
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United States of America Patent
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-
Sep 15, 1987
Grant Date -
N/A
app pub date -
Oct 10, 1985
filing date -
Dec 12, 1984
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A microprocessor system is disclosed wherein a microprocessor has a multiplexed address/data bus which communicates with a plurality of memory and input/output devices. A demultiplexing register permits the demultiplexing of the microprocessor address/data bus, while a decoder permits the selection of one of the system devices during a microprocessor external operation in response to the most significant address bits. The system output devices comprise a plurality of TTL outputs whose inputs are connected to the output of a demultiplexing register where, during a microprocessor external operation, information representative of the less significant address portion is latched. Datum information transfer to an output TTL gate is obtained by having an external operation executed by the microprocessor so that the most significant address bits select the gate and the less significant address portion represents the datum to be transferred.
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