Dual redundant bus interface circuit architecture
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United States of America Patent
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-
Sep 22, 1987
Grant Date -
N/A
app pub date -
Jul 30, 1984
filing date -
Jul 30, 1984
priority date (Note) -
Expired
status (Latency Note)
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Abstract
An asynchronous bus interface circuit manages the transfer of messages between a host processor memory, and one of two redundant serial data buses by separately processing command words thereby permitting efficient handling of status and data words.
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