Test circuitry for testing fuse link programmable memory devices
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United States of America Patent
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-
Oct 6, 1987
Grant Date -
N/A
app pub date -
Mar 21, 1986
filing date -
Mar 21, 1986
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A testing circuit for testing fuse elements in programmable memory devices. The circuit provides for testing whether the fuses have the proper resistance, both after manufacturing and after programming of the memory device. The testing circuit includes a current varying means which may include either a variable resistance or a variable current sink. The variable resistance is connected to a fuse element to form a voltage divider with the same. A sensing amplifier is connected at a node therebetween for sensing the current through the fuse element and, thus, the resistance of the same. The variable current sink provides variable current levels, thereby achieving the same above results.
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