Method for detecting intermittent error in volatile memory
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United States of America Patent
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-
Oct 6, 1987
Grant Date -
N/A
app pub date -
Dec 5, 1985
filing date -
Dec 14, 1984
priority date (Note) -
Expired
status (Latency Note)
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Abstract
Primary and secondary data save areas are established in a volatile memory (CMOS) which is backed up with a battery. The same predetermined data are stored in the primary and secondary data areas together with check sum. At a power on time, the data of the primary area are added together and the data of the secondary area are added together. When both of results of the addition are equal to the check sum, no error is detected. When only one of results of addition is different from the check sum, an intermittent error is detected. When both of results of addition are different from the check sum, battery exhausted condition is detected. If the intermittent error is detected, data of one area whose result of addition is equal to the check sum are copied to other area whose result addition is different from the check sum.
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