Computer system capable of interruption using special protection code for write interruption region of memory device
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United States of America Patent
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-
Oct 20, 1987
Grant Date -
N/A
app pub date -
Jan 17, 1986
filing date -
Jan 19, 1985
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A computer system capable of interruption using a special protection code for a write interruption region of a main memory, including a subsidiary memory connected with a central processor unit and the main memory. The subsidiary memory delivers a translated real address code and protection codes including ordinary protection codes and the special protection code. Checking of the special protection code in the special protection code check number is carried out when the special protection code from the subsidiary memory is present and an access instruction from the central processor unit is a write instruction. Thereby, writing into a region beyond a stack region in the main memory is possible and the information of execution of the write interruption to the region beyond the stack region in the main memory is transmitted to the central processor unit.
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