Importance

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Abstract

An apparatus for controlling sequential (DMA) transfers between a plurality of buffer memories and a data translation device. Each buffer has an overrun has an overrun area associated with it. Prior to transfers from the buffers to the data translation device, the buffer memories are first 'threaded' together by loading the overrun area of a first buffer with data from the next buffer. During the DMA transfer, when the first buffer becomes empty a request is made to the computer to restart the DMA operation on the next sequential buffer, but while the interrupt is being serviced data is continually being transferred out of the first buffer's overrun area. Alternatively, for transfers from the data translation device to the buffers, after the first buffer is full, an interrupt is generated and incoming data is stored in the first buffer's overrun area while the interrupt is being serviced. After the interrupt is serviced data is stored in the next sequential buffer. Subsequently, the computer determines the exact point where the DMA process stopped depositing data in the overrun area by sequentially examining the entries in the overrun area. The computer then moves the data in the overrun area into the next buffer to complete the transfer.

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First Claim