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Abstract

A non-volatile random access memory (NVRAM) cell including a volatile static type random access memory cell consisting of a flop-flip circuit having two nodes on which a paired bit signal are accessed and a non-volatile electrically erasable programmable read-only memory (EEPROM) cell consisting of a memory transistor having a floating gate, a capacitor circuit, on which a voltage called as a writing voltage is applied, including a tunnel capacitor, and two transistors for determining the polarity of the charge being to be stored at the floating gate with a tunnel current in the tunnel capacitor corresponding to the level of the bit signal existing at one of the two nodes in the flip-flop circuit. When the power supply voltage of the NVRAM cell is turned off, the EEPROM cell stores the positive or negative charge at the floating gate corresponding to the bit signal level at the node in the flip-flop circuit holding the charge after the power supply voltage and the writing voltage are turned off. When the power supply voltage is turned on, the EEPROM cell recalls the state of the flip-flop circuit so as to be same as before using the charge stored at the floating gate.

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First Claim