Parity detection system for wide bus circuitry
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United States of America Patent
Stats
-
Dec 1, 1987
Grant Date -
N/A
app pub date -
Apr 4, 1986
filing date -
Apr 4, 1986
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A parity checking system for establishing integrity of data transfer on a wide bus. Each set of '4' bus lines of a multiple line bus is passed from a driver chip to a corresponding receiver chip. An added parity driver chip senses each corresponding bit line of each driver chip to develop a set of four parity signals for comparison with corresponding parity signals from each corresponding bit line of each one of a set of receiver chips. Any discrepancy will generate a parity error signal.
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