Digital frame processor pipe line circuit
Number of patents in Portfolio can not be more than 2000
United States of America Patent
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-
Dec 1, 1987
Issued Date -
N/A
app pub date -
Nov 12, 1986
filing date -
Jan 4, 1984
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A plurality of digital words representing picture elements are sequentially loaded into a readin register, which words are thereafter written in parallel into a random access memory via a write data register. The words are subsequently readout of the random access memory in parallel into a read data register and to a readout data register which thereafter sequentially transmits the words stored therein to an output circuit. The arrangement is such that each word may flow through the pipeline to be processed during a clock period of P ns; although the RAM response time is greater than P ns.
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