Matrix multiplication circuit for graphic display
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United States of America Patent
Stats
-
Jan 12, 1988
Grant Date -
N/A
app pub date -
May 7, 1984
filing date -
May 6, 1983
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A matrices elements memory is constituted by random access memories, and its addresses are divided into a high address and a low address. The high address specifies areas holding matrix elements, and the low addresses of the matrix elements are designated sequentially bit-by-bit, starting from the least significant bit, so as to enable serial reading. A calculation unit consists of pairs of serial multiplicators which are either used in a cascade connection or independently as independent multiplicators, in order to correspond to the data length of a multiplicand.
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