Importance

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Abstract

An array reconfiguration apparatus is employed in large integrated circuits and large systems. The apparatus makes use of spare wires and/or computation elements which are incorporated in the array. The apparatus uses spare wires in place of defective wires and/or the apparatus uses spare computation elements in place of defective computation elements so that an operational system may be created in spite of the occurrence of numerous manufacturing or lifetime faults. The excess wires are utilized as data input and output lines and as such each data line is associated with a bidirectional buffer/receiver (B/R). The bidirectional B/R's are capable of transmitting data in either direction as from an input terminal to an output terminal or vice versa. Each data line is connected to a bidirectional multiplexing device which has a control input. Control logic means has dynamically stored therein the assignment of each significant wire and each computation element. Only unreliable wires as between integrated circuits are switchable. The control logic selects operational elements as well as operational data lines and hence uses the spare data lines to make connections between the redundant elements on the circuit board so that an array configuration can be implemented in spite of multiple defects on the overall circuit board. The invention further discloses a simple method for computing the assignments of cells and wires to avoid the defects.

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First Claim