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Abstract

A video RAM write control apparatus cmprises a video RAM of byte access for storing dot pattern data, and a write circuit for supplying write data of one byte and a write enable signal to the video RAM. The video RAM includes n (n being an arbitrary natural number) memory blocks, each consisting of 1 bit.times.N addresses, the same address being assigned to the n-bits word. The write circuit includes a bit mask register in which an n-bit bit mask pattern data having a flag in a specific bit is set, and NAND gates for supplying AND signals of an output of each bit of the bit mask register and a write enable signal to the write enable terminal of each memory block.

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First Claim