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Abstract

A system for simultaneous transmission of data blocks or vectors between a memory and one or a number of data-processing units having a memory which is subdivided into a whole number N of logic arrays of n physical arrays of q memory locations. An interconnection network controlled by a control logic device establishes the connections between the logic arrays of the memory and the data-processing units. Addressing devices controlled respectively by a data-processing unit have the function of addressing the memory locations to which each data-processing unit requests access. The control logic device has logic for establishing a connection between each requesting unit and the logic array containing the address of the start of the vector or data block to be transferred and control means for successively switching the requesting unit to the following logic arrays at the end of each data transfer between a logic array of the memory and the requesting data-processing unit.

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First Claim