Importance

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Abstract

A memory system for use in a computer which in the preferred embodiment provides two megabytes of capacity per board (up to four boards) is disclosed. An ALU generates an address signal which selects a number of set locations in the main memory. Simultaneously, a portion of the address field is fed to a set association logic circuit for parallel processing. The set association circuit contains tag storage memories and comparators which store tag values. These values are compared with address fields, and if a match occurs, one of the comparators selects a 128-bit word from the main memory. A hash function is also used to provide for dispersal of storage locations to reduce the number of collisions of frequently used addresses. Because of hardware implementation of hashing and least recently used (LRU) algorithm, a constant predetermined cycle time is realized since all accessing functions occur substantially in parallel. Several sets of data are accessed simultaneously while a set association process is performed which selects one of the accessed sets, wherein access time is reduced because of the parallel accessing.

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First Claim