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Abstract

A plurality of identical processor cells arranged interconnected to form a data processor for processing digital data signals. Each of the cells includes an arithmetic processing element having three input terminals and two arithmetic output terminals. A plurality of memories connected to said arithmetic processing element are individually controllable to supply selected ones of a plurality of predetermined data signals to the input terminals of said processing element in response to control signals from a controller. The memories are connected to the arithmetic processing element and the controller such that both logical and arithmetic operations are performed by the arithmetic element. The data processor includes n times m cells interconnected in an m by n matrix with interior cells and edge cells. The arithmetic processing element, preferably is a full adder having two data input terminals, a carry input terminal, a sum output terminal and a carry output terminal, and the plurality of memories includes first, second and third single-bit data registers, each selectively controllable to load one of the plurality of predetermined data signals, and a multi-bit memory such as a RAM having an output terminal and selectively addressable storage locations.

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First Claim