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Abstract

Hybrid parallel internally pipelined Vector Image Processors (24, 41, 54) which may also be externally pipelined. The exemplary Processors (24, 41, 54) include n processing elements (PE.sub.a -PE.sub.n)--wherein 'n' is any whole integer but, when greater than '1', the elements are arranged in parallel in a one-dimensional column--for processing a two-dimensional XY PIXEL image array (25, 25', 38, 52) wherein each element (PE.sub.a -PE.sub.n) includes: (i) multiple cascaded latches (N1, N2, N3) in a one-dimensional row; (ii) a neighborhood functional unit (NFU.sub.n) for performing NEIGHBORHOOD TRANSFORMS; (iii) an arithmetic logic unit (ALU) for performing ARTIHMETIC/LOGIC TRANSFORMS; (iv) means (48.sub.n, 49.sub.n, 50.sub.n) for transferring data in the latches (N1, N2, N3) to the neighborhood functional unit (NFU.sub.n) and to the neighboring north/south processors; (v) means (48.sub.n, 49.sub.n) for transferring data in the latches (N1, N2) to the arithmetic logic unit (ALU); and (vi), means (48.sub.n-1 . . . 50.sub.n-1, 48.sub.n+1 . . . 50.sub.n+ 1) for inputting image boundary and PIXEL neighbor data to the neighborhood functional unit (NFU.sub.n). Where the number of rows ('X') of PIXEL data is greater than the number ('n') of processors (PE.sub.a -PE.sub.n), the system processes adjacent strips (38.sub.a -38.sub.d) of PIXEL rows with all PIXELS in a given column ('Y') within each strip (38.sub.a -38.sub.d) being processed in parallel and with all columns of PIXELS in each strip being processed in internally pipelined form. This latter system includes border Memories (22.sub.NB, 22.sub.SB) for storing boundary data for each strip (38.sub.a -38.sub.d) and for cross-feeding the north and south rows of PIXEL output data in each strip to respective ones of the border Memories (22.sub.SB, 22.sub.NB) for use in processing adjacent strips.

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