Importance

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Abstract

A method of fabricating a plurality of electronic circuits with transistors in schematic form in a customizable semiconductor integrated device, such as a base array, is disclosed. The base array has a plurality of chains of continuously electrically connected transistors, all of the same type, with the drain of a transistor connected to the source of an adjacent transistor. The schematic transistors are grouped by diffusion line tracing to form a plurality of groups. Each group of schematic transistors is assigned to physical transistors in the base array. The cost function associated with each group of physical transistors is calculated. The total cost function is optimized by changing the assignment of one or more groups of the schematic transistors to the physical transistors. The electrical interconnection from one group of physical transistors to another group of physical transistors is routed to form the physical layout of the circuit. Isolation transistors are also provided to isolate physical layouts of the circuit from one another or to provide isolation between groups of physical transistors where isolation is needed. The gate of each isolation transistors is connected to a voltage source thereby isolating the physical layouts of the circuits.

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First Claim