Video display system using memory with parallel and serial access employing serial shift registers selected by column address
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United States of America Patent
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-
May 24, 1988
Grant Date -
N/A
app pub date -
Dec 30, 1983
filing date -
Dec 30, 1983
priority date (Note) -
Expired
status (Latency Note)
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Abstract
In a video-type computer system and the like, an improved memory circuit is provided for adapting the system to CRT screens having different resolutions. The memory circuit includes a bit-mapped RAM unit or chip having sufficient cells to accommodate any CRT screen sought to be used, and also a shift register having taps at a plurality of different locations corresponding to different columns of cells in the RAM unit. When the RAM unit is in serial mode, column address to the RAM unit is also used to instruct and actuate a suitable decoder circuit to select the tap appropriate to unload the portion of the shift register containing only the data bits of interest.
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