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Abstract

A pseudo-random binary sequence generator comprises at least one shift register (S, T) arranged in a recirculating loop and having a plurality of logic gates (G) for logically combining the outputs of selected stages of the register to provide a pseudo-random sequence, and a multiplexer (M), having a p data inputs and q address inputs all connected to selected shift register stages, and which selects at any instant one of the p data input bits in accordance with the q-bit address word to provide the generator output. The number s of logic gates is especially high and is related to the total number r of shift register stages (r>p+q) by the expression: 2.sup.s .gtoreq.r.sup.2. Some of the shift register stages of the or each shift register are connected to selected data inputs of the multiplexer and others of the stages of the same shift register are connected to selected address inputs of the multiplexer. Switches (SW1-SW4) are provided for regularly loading a re-initialization word into the shift register(s), and this re-initialization word can be formed by an arrangement (FIG. 4) which combines a control word with the frame count.

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