Processor utilizing reconfigurable process segments to accomodate data word length
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United States of America Patent
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May 31, 1988
Grant Date -
N/A
app pub date -
Dec 26, 1985
filing date -
Dec 26, 1985
priority date (Note) -
Expired
status (Latency Note)
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Abstract
An independently programmable, parallel processor for electronic computers for performing mathematical and logical operations is provided having an array of arithmetic-logic units which are interconnected so as to form dynamically reconfigurable segments of arithmetic-logic units within the array. These dynamically reconfigurable segments are formed by particular combinations of the arithmetic-logic units and are so combined with selective switching circuitry so as to provide the processor with its independent and parallel features.
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