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Abstract

A frame synchronizing circuit uses parallel processing of a received multiplexed signal to detect frame synchronization. The input signal is separated into a predetermined number of signal trains. A matching number of frame synchronizing pattern detection circuits detect the presence of the frame synchronizing pattern by each of the frame synchronizing pattern detection circuits detecting the presence of a modified frame synchronizing pattern. The modified frame synchronizing patterns all contain the same sequence of bits, but the leading bit of the frame synchronizing pattern is in a different signal train in each of the modified frame synchronizing patterns. Timing comparison circuits corresponding to the modified frame synchronizing pattern detection circuits indicate which, if any, of the modified frame synchronizing patterns, are in coincidence with a frame pulse generated at the time the frame synchronizing pattern is expected to be detected. Synchronization guarding circuits corresponding to the timing comparison circuits indicate which, if any, of the modified frame synchronizing patterns is in synchronization with the frame pulse. A timing control circuit adjusts the timing of the frame pulse when the timing comparsion and synchronization guarding circuits indicate noncoincidence and asynchronization of all of the modified frame synchronizing patterns.

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