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Abstract

A programmable FIFO buffer is disclosed which including a (serial) input register, a control register, a (parallel-input parallel-output-type) FIFO buffer, a (serial) output register, and another control register. The input register is for receiving signals representing in serial format a word of data and for developing signals representing the data word converted to parallel format. The former control register is for controlling the serial-to-parallel conversion process. The (parallel-input parallel-output-type) FIFO buffer is for storing the data word. The output register is for receiving from the buffer, signals representing in parallel format a word of data stored in the buffer and for developing signals representing the stored data word converted to serial format. And, the latter control register is for controlling the parallel-to-serial conversion process.

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First Claim