Digital data processor apparatus with pipelined fault tolerant bus protocol

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United States of America Patent

PATENT NO 4750177
SERIAL NO

06904827

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Abstract

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A fault-tolerant computer system provides information transfers between the units of a computing module, including a processor unit and a memory unit and one or more peripheral control units, on a bus structure common to all the units. Information-handling parts of the system, both in the bus structure and in each unit, can have a duplicate partner. Error detectors check the operation of the bus structure and of each system unit to provide information transfers only on fault-free bus conductors and between fault-free units. The computer system can operate in this manner essentially without interruption in the event of faults by using only fault-free conductors and functional units. Arbitration circuits of unusual speed and simplicity provide units of the computing module with access to the common bus structure according to the priority of each unit. The units of a module check incoming and outgoing signals for errors, signal other module units of a detected error, and disable the unit from sending potentially erroneous information onto the bus structure.

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Patent Owner(s)

Patent OwnerAddress
STRATUS COMPUTER INCMARLBORO MASSACHUSETTS 01752

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Baty, Kurt F Medway, MA 10 516
Dynneson, Ronald E Brighton, MA 4 424
Falkoff, Daniel M Natick, MA 3 235
Hendrie, Gardner C Marlboro, MA 4 331
Reid, Robert Dunstable, MA 36 1706
Samson, Joseph E Dover, MA 4 382
Wolff, Kenneth T Medway, MA 6 392

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