Static semiconductor memory device comprising word lines each operating at three different voltage levels
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United States of America Patent
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Jun 14, 1988
Grant Date -
N/A
app pub date -
Sep 3, 1985
filing date -
Oct 22, 1984
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A semiconductor memory device in accordance with the present invention operates in response to an address transition detection (ATD) signal for detecting a change in an x address as well as to a write enable signal WE to make the signal level on a selected word line vary according to the read mode and the write mode, whereby dissipation of electric power can be reduced.
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