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Abstract

A transaction analyzer, for use in conjunction with a data acquisition system having a probe for accessing binary data, i.e. address and control signals appearing at the terminals of an operating microprocessor, determines the type of processor transaction occurring based on sequences of state changes occurring on a selected set of the control signals so accessed. The transaction analyzer then generates a binary number representing the transaction type which may be acquired by the acquisition system in conjunction with the data accessed by the probe. The transaction analyzer, which uses an asychronous state machine, also generates control signals used by the acquisition system to clock data storage along with a signal to control the direction of flow of data signals between the processor and the acquisition system. The transaction analyzer is programmable such that it may be used with a variety of different types of microprocessors which may be accessed by the probe, even though such microprocessors may generate differing control line state change patterns during processor transactions and even though transaction types may vary from processor to processor.

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First Claim