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Abstract

A method of operating a semiconductor memory with a facility for performing integrated parallel testing, wherein the semiconductor memory is subdivided into n identical cell fields with addressable storage cells, each of the storage cells of each of the cell fields being addressable within a storage cycle simultaneously with, respectively, one storage cell of each of the other cell fields, wherein during a testing operation of the semiconductor memory, the storage cell of one of the n cell fields addressed for the purpose of reading out (read cycle) of a stored test datum has, due to a writing-in process, the same stored test datum as each of the other addressed storage cells addressed in the same read cycle in the case ('go' case) wherein the semiconductor memory is in order, which comprises, within the semiconductor memory, in the testing operation, simultaneously comparing within a read cycle, the test data read out from each of the storage cells addressed within the read cycle of the respective n cell fields, with a reference data signal which is identical with the original test data to be stored; and alternatively in a 'go' case, via the semiconductor memory, making available a signal with a first waveform at a semiconductor memory terminal; and in a 'no-go' case, via the semiconductor memory, making available a signal with a second waveform at the semiconductor terminal; and evaluation circuit for performing the method.

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