Solid state interconnection system for three dimensional integrated circuit structures
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United States of America Patent
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-
Jun 28, 1988
Grant Date -
N/A
app pub date -
Jun 3, 1982
filing date -
Jun 3, 1982
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A semiconductor circuit apparatus including several semiconductor substrates interconnected by having elevated portions of one substrate contacting the surface of the second substrate where both substrates include at least one electrical circuit. Also included is a method for forming this three dimensional integrated circuit structure by forming the elevated portions of the semiconductor substrate by applying an orientation-dependent etch and then applying an electrically conductive coating to this elevated portion. Electrically conductive bonding pads are formed on the second semiconductor substrate. These pads are selectively positioned relative to the elevated portions formed on the first semiconductor substrate. Contacts between the first and second substrate are formed by forming bonds between the elevated portions on the one substrate and the electrically conductive pads on the second substrate.
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