Progressive insertion placement of elements on an integrated circuit
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United States of America Patent
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-
Jun 28, 1988
Grant Date -
N/A
app pub date -
Nov 21, 1985
filing date -
Nov 21, 1985
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A method of placing circuit elements in an integrated circuit. The chip area is divided into a grid. In an initial pass, the elements are randomly placed in the grid locations, and these placements are recorded. Thereafter, the elements are sequentially replaced in each of the grid locations, and a score is calculated for the wiring interconnections to the remaining elements as they were last recorded. The placement yielding the best score is recorded for that element. This placement is repeated for each of the elements. Once all the elements have been replaced, a final score is compared with the last best score. If the recent final score is better, the placements associated with that score are saved as the best placements. Then the process of replacement is repeated until a given number of iterations fails to yield a better score.
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