
US Patent No: 4,757,441
Number of patents in Portfolio can not be more than 2000
Logical arrangement for controlling use of different system displays by main proessor and coprocessor
Stats
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Jul 12, 1988
Issued date -
Jun 29, 1987
filing date -
07/068,769
serial no -
Expired
status
Importance
Abstract
A method and system for controlling the display of data in a data processing system that includes a main processor, a memory subsystem, and an Input/Output subsystem which includes an I/O Channel Controller for managing traffic on an I/O bus having an attached co-processor and a plurality of I/O devices including display devices with different reserved I/O address space. The main processor can establish different display modes for displays having different reserved I/O address space, which generally indicates different display types. In one mode, a display is assigned exclusively to the main processor and attempted data transfers by the co-processor to that display are suppressed. The display control means is based on logic circuitry associated with the co-processor for trapping instructions having addresses within the range of those reserved for the display devices. The logic enables normal writes and reads to the video buffer to be suppressed or relocated to the virtual buffer, depending on the mode established by the main processor. A circular queue is established in memory to enable the main processor to selectively individually update the video buffer with the changes that have been made to the virtual buffer.
First Claim
Related Publications
International Classification(s)
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Cited Art
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