Method and apparatus for validating prefetched instruction
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United States of America Patent
Stats
-
Jul 12, 1988
Issued Date -
N/A
app pub date -
Jul 29, 1987
filing date -
Sep 12, 1983
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A method and data processing system for validating prefetch instruction. The system includes an instruction unit, an n-stage pipeline which provides data segments representing instruction words from a memory to the instruction unit. The system further includes a circuit for prefetching instruction words to be executed subsequently to a presently executing instruction and a circuit for verifying the validity of the prefetched instruction word prior to execution thereof by the execution unit, and a circuit for causing the instruction unit to a fault condition only when the execution of an invalid instruction is begun.
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