Parallel-to-serial converter
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United States of America Patent
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-
Jul 19, 1988
Grant Date -
N/A
app pub date -
Mar 9, 1987
filing date -
Mar 8, 1986
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A parallel-to-serial converter is described, comprising a shift register into which a data word can be loaded in parallel and then shifted out serially. As the data is shifted out, a string of zeros is shifted in. When a predetermined number of zeros is detected, a flip-flop is set at the next clock beat. This switches the shift register into its parallel load mode so that, at the next again clock beat the shift register is parallel loaded with the next data word. The detection of the predetermined number of zeros and the setting up of the shift register occur in different clock periods, allowing the clock period to be reduced, thus increasing the speed of operation.
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