Memory management unit for addressing an expanded memory in groups of non-contiguous blocks
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Aug 2, 1988
Grant Date -
N/A
app pub date -
Jan 2, 1986
filing date -
Jan 2, 1986
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A n-channel memory management circuit operates as an interface unit between a microprocessor, which microprocessor is normally capable of addressing only 64K bytes of memory, to provide expandable memory configurations with a memory capacity of at least 128K bytes of read only memory (ROM) and 128K bytes of random access memory (RAM) which are directly accessed by the microprocessor in 64K bytes blocks or 'windows' consisting of smaller size non-contiguous blocks from the entire memory configuration.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully