Importance

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Abstract

A data processing system, wherein the central processing unit has an arithmetic element for processing data in response to machine program instructions and a control store for microcode program storage responsive to the machine instructions for implementing the instruction, has an improved arithmetic unit for enabling higher throughput without substantially increasing hardware cost. The arithmetic unit has a reconfigurable arithmetic logic unit which is controlled in response to both hardware generated data signals and microcode generated data signals. A data string manipulation circuitry provides for aligning data strings for processing by the arithmetic logic unit. Circuitry is provided, responsive to a decoded machine instruction, for generating control signals for configuring the arithmetic unit and for controlling the data string manipulation circuitry. As a result, the number of microcode steps needed to implement particular decimal and string manipulation machine instructions is significantly reduced, thereby saving machine cycles, while the additional hardware cost is very modest.

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First Claim