US Patent No: 4,766,086

Number of patents in Portfolio can not be more than 2000

Method of gettering a semiconductor device and forming an isolation region therein

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Abstract

In a method of manufacturing a semiconductor device according to the present invention, a given position of a thermal oxide film formed on a monocrystalline silicon layer is opened to expose a surface of the monocrystalline silicon layer to serve as a getter site, a polycrystalline silicon layer is deposited on the thermal oxide film and the surface of the monocrystalline silicon layer, and the polycrystalline silicon layer is oxidized to convert the surface of the monocrystalline silicon layer directly contacting the polycrystalline silicon layer into an oxide film by thermal oxidation. That is, the position of interface between the oxide film and the monocrystalline silicon layer is shifted into the original monocrystalline silicon layer. During thermal oxidation of the polycrystalline silicon layer, a plurality of crystal defects to serve as getter sites are generated deeper than those generated by a conventional implagetter method in the monocrystalline silicon layer. In addition, the crystal defects generated in the manner described above do not extend to the surrounding region by subsequent annealing so that a region of the crystal defects is limited.

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First Claim

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Patent Owner(s)

Patent OwnerAddressTotal Patents
KABUSHIKI KAISHA TOSHIBATOKYO36116

International Classification(s)

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  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Aoyama, Masaharu Fujisawa, JP 19 625
Ito, Toshiyo Yokohama, JP 2 102
Ohshima, Jiro Kitakyushu, JP 17 341
Taka, Shin-ichi Kitakyushu, JP 14 317

Cited Art

Patent Info (Count) # Cites Year
 
HITACHI, LTD. (1)
4,640,721 Method of forming bipolar transistors with graft base regions 20 1985
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (1)
4,437,897 Fabrication process for a shallow emitter/base transistor using same polycrystalline layer 19 1982
 
MICRON SEMICONDUCTOR, INC. (1)
4,389,255 Method of forming buried collector for bipolar transistor in a semiconductor by selective implantation of poly-si followed by oxidation and etch-off 12 1980
 
NATIONAL SEMICONDUCTOR CORPORATION (1)
4,322,882 Method for making an integrated injection logic structure including a self-aligned base contact 11 1980
 
SIEMENS AKTIENGESELLSCHAFT (1)
4,581,319 Method for the manufacture of bipolar transistor structures with self-adjusting emitter and base regions for extreme high frequency circuits 29 1984

Patent Citation Ranking

Forward Cites

Patent Info (Count) # Cites Year
 
SILICON GENESIS CORPORATION (24)
6,511,899 Controlled cleavage process using pressurized fluid 48 1999
6,528,391 Controlled cleavage process and device for patterned films 76 1999
6,632,724 Controlled cleaving process 44 2000
6,544,862 Particle distribution method and resulting structure for a layer transfer process 21 2000
6,558,802 Silicon-on-silicon hybrid wafer assembly 27 2000
6,500,732 Cleaving process to fabricate multilayered substrates using low implantation doses 47 2000
6,548,382 Gettering technique for wafers made using a controlled cleaving process 55 2000
6,458,672 Controlled cleavage process and resulting device using beta annealing 42 2000
6,486,041 Method and device for controlled cleaving process 49 2001
6,513,564 Nozzle for cleaving substrates 41 2001
6,790,747 Method and device for controlled cleaving process 64 2002
7,056,808 Cleaving process to fabricate multilayered substrates using low implantation doses 19 2002
6,890,838 Gettering technique for wafers made using a controlled cleaving process 20 2003
7,160,790 Controlled cleaving process 12 2003
7,348,258 Method and device for controlled cleaving process 14 2004
7,371,660 Controlled cleaving process 28 2005
7,759,217 Controlled process and resulting device 0 2007
7,410,887 Controlled process and resulting device 2 2007
7,776,717 Controlled process and resulting device 1 2007
7,811,900 Method and structure for fabricating solar cells using a thick layer transfer process 3 2007
7,846,818 Controlled process and resulting device 0 2008
8,293,619 Layer transfer of films utilizing controlled propagation 0 2009
8,330,126 Race track configuration and method for wafering silicon solar substrates 0 2009
8,329,557 Techniques for forming thin films by implantation with reduced channeling 0 2010
 
SONY CORPORATION (3)
5,734,195 Semiconductor wafer for epitaxially grown devices having a sub-surface getter region 16 1996
5,874,348 Semiconductor wafer and method of manufacturing same 13 1996
6,140,213 Semiconductor wafer and method of manufacturing same 5 1998
 
KABUSHIKI KAISHA TOSHIBA (2)
5,289,031 Semiconductor device capable of blocking contaminants 4 1992
5,874,325 Method of manufacturing semiconductor device with gettering and isolation 14 1996
 
MITSUBISHI DENKI KABUSHIKI KAISHA (1)
5,721,145 Method of making a semiconductor substrate having gettering effect 10 1996
 
NEC CORPORATION (1)
5,444,001 Method of manufacturing a semiconductor device readily capable of removing contaminants from a silicon substrate 24 1993
 
NEC ELECTRONICS CORPORATION (1)
5,895,236 Semiconductor device fabricating method having a gettering step 3 1997
 
NIKON CORPORATION (1)
7,470,944 Solid-state image sensor 3 2004
 
SEH AMERICA, INC. (1)
6,576,501 Double side polished wafers having external gettering sites, and method of producing same 1 2002
 
TEXAS INSTRUMENTS INCORPORATED (1)
4,877,748 Bipolar process for forming shallow NPN emitters 11 1989
 
OTHER [CHECK PATENT PROFILE FOR ASSIGNMENT INFORMATION] (1)
6,413,837 Controlled cleavage process and device for patterned films 1999