Test board for semiconductor packages

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 4766371
SERIAL NO

06875517

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Abstract

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A test device for burn-in tests of semiconductor packages. The device includes a printed circuit board provided with openings or frames for receiving the semiconductor packages to be tested and aligning the package lead with circuit board terminals. A cover plate provided with elastic bodies on a back side thereof is used to concurrently elastically press all of the leads and terminals into electrical contact. In one embodiment, elastic connectors having thin metal wires embedded therein are provided in the openings or frames to electrically connect the leads to the terminals when the cover plates is pressed downwards on the semiconductor packages.

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Patent Owner(s)

Patent OwnerAddress
RISHO KOGYO CO LTD1-9 DOJIMA 2-CHOME KITA-KU OSAKA-SHI OSAKA 5300003 ?5300003

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Moriya, Tadashi Osaka, JP 8 130

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