Method for making planar vertical channel DMOS structures
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United States of America Patent
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-
Aug 30, 1988
Issued Date -
N/A
app pub date -
Mar 24, 1986
filing date -
Mar 24, 1986
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A DMOS power transistor has a vertical gate and a planar top surface. A vertical gate fills a rectangular groove lined with a dielectric material which extends downward so that source and body regions lie on each side of the dielectric groove. Carriers flow vertically between source and body regions and the structure has a flat surface for all masking steps.
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