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Abstract

Built-in self-test programmable logic arrays use a deterministic test pattern generator to generate test patterns such that each cross point in an AND-plane can be evaulated sequentially. A multiple input signature register which uses X.sup.Q +1 as its characteristic polynomial is used to evaulate the test results, where Q is the number of outputs. The final signature can be further compressed into only one bit. Instead of only determining the probability of fault detection, in this scheme, the fault detection capability has been analyzed using both the stuck at fault and the contact fault model. It can be shown that all of these faults can be detected. Shorts between two adjacent lines can be detected by using NOR gates.

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First Claim