Digital signal processor with parallel multipliers
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United States of America Patent
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-
Sep 13, 1988
Grant Date -
N/A
app pub date -
Oct 21, 1986
filing date -
Oct 23, 1985
priority date (Note) -
Expired
status (Latency Note)
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Abstract
An arithmetic operation portion 3 comprises a plurality of multipliers 311 and 312 connected directly with a memory portion 1 so that multiplication processing can be performed in parallel. As a result, the processing capacity for multiplication and addition can be increased and the throughput rate of data can be improved.
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