Wafer alignment and positioning apparatus for chip testing by voltage contrast electron microscopy
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United States of America Patent
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Sep 20, 1988
Grant Date -
N/A
app pub date -
Dec 29, 1986
filing date -
Dec 29, 1986
priority date (Note) -
Expired
status (Latency Note)
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Abstract
An apparatus for use in testing IC chips on a semiconductor wafer is disclosed that allows the wafer and an electrical probe to be independently positioned and then clamped together and moved as a single unit when they are in alignment. This permits a chip on a wafer to be supplied with power and tested electronically while any desired area of the chip can be positioned in the field of view of a scanning electron microscope for examination, such as with a voltage-contrast secondary-electron detector. Use of the disclosed apparatus will greatly facilitate and simplify the testing of unbonded chips on semiconductor wafers.
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