Importance

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Abstract

A bus arbitration controller controls access of a plurality of asynchronous potential master devices to a unitary interconnecting bus by forming a distributed state machine of arbitration logic units in each of the potential master devices. Each arbitration logic unit receives control signals by way of the unitary bus which are common to all the devices, each control signal being the logical OR of the corresponding signals from all other devices. The control signals include a device address/priority number and a synchronization signal set. The arbitration logic includes a priority resolver which awards bus access to a device having the highest address/priority number, and control logic which receives the common synchronization signal set and synchronizes the operation of the device in which the arbitration logic resides with all other devices contending for the unitary bus. The control logic and the priority resolver are programmable array logic circuits.

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First Claim