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Abstract

Static content addressable memory cells (CAMs) combining six transistors and two pairs of control signal lines, where both pairs of lines provide dual functions and where the content addressing function is provided by a unique combination of control and precharge signals on the four control signal lines. An alternate CAM embodiment comprising eight transistors and an additional interrogation signal line is also disclosed. The disclosed content addressable memory cells are preferably implemented by complementary metal oxide field effect transistors (CMOSFETs) and have particular application in very large scale integrated (VLSI) chips, where small cell size is of high importance and/or where high operational speed, reliability, radiation hardness and/or noise immunity, and/or operation at high temperatures and/or a large supply voltage range is required.

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First Claim