Process for fabricating electrically alterable floating gate memory devices
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United States of America Patent
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Oct 25, 1988
Grant Date -
N/A
app pub date -
Sep 28, 1987
filing date -
Sep 28, 1987
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A process for fabricating contactless electrically programmable and electrically erasable memory cells of the flash EPROM type. The contactless cells use elongated source and drain regions disposed beneath field oxide regions. The drain regions are shallow compared to the source regions. The source regions have more graded junctions. Floating gates are formed over a tunnel oxide (120 .ANG. thick) between the source and drain regions with word lines being disposed perpendicular to the source and drain regions. One dimension of the floating gates is formed after the word lines have been patterned by etching the first layer of polysilicon in alignment with the word lines.
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