Wait mode power reduction system and method for data processor
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United States of America Patent
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Oct 25, 1988
Issued Date -
N/A
app pub date -
Oct 13, 1987
filing date -
Nov 7, 1983
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A method and apparatus for reducing power consumption in a data processing system by interrupting the supply of clocking pulses to selected portions of the system in response to a power-down signal provided by a data processing portion of the system only if the state of a respective control signal indicates that that particular portion of the system is then disabled or otherwise inhibited from interrupting the operation of the data processing portion.
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